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fn8092 rev 6.00 page 1 of 16 november 30, 2015 fn8092 rev 6.00 november 30, 2015 isl88705, isl88706 , isl88707, isl88708 , isl88716, isl88813 datasheet designed with high reset threshold accuracy and low power consumption, the isl88 705, isl88706, isl88707, isl88708, isl88716 and isl88813 devices are microprocessor supervisors th at are designed to monitor power-supply and battery func tions in microprocessor systems. they can help to low er system cost, reduce board space requirements and increa se the reliability of systems. these devices provide essent ial functions such as supply voltage supervision by asserting a reset output during power-up and power-down as well as during brownout conditions. an auxiliary volt age monitor is provided for detecting power failu res warning the syst em of low battery conditions or presence det ection. in addition, an independent watchdog time r helps to monitor microprocessor activity every 1 .6s (typical). an active-low manual reset is offered and reset signals remain asserted until v dd returns to proper operating levels. users can increase the nominal 200ms power-on reset time-out delay by adding an external capacitor to the c por pin on the isl88707 and isl88708. features ? fixed-voltage options allow precise monitoring of +3.0v, +3.3v, and +5.0v power supplies ? additional voltage monitor for power-fail detection or low-battery warning - monitors voltages down to 1.25v - adjustable power-fail input threshold ? watchdog timer capability with 1.6s time-out ? both rst and rst outputs available ? 140ms minimum reset pulse width with option to customize using an external capacitor ? manual reset input on all devices ? reset signal valid down to v dd = 1v ? accurate 1.8% voltage threshold ? immune to power-supply transients ? ultra low 10a maximu m supply current at 3v ? pb-free (rohs compliant) applications ? portable/battery powered equipment ? notebook/desktop computer systems ? designs using dsps, microcontrollers or microprocessors ? controllers ? intelligent instruments ? communications systems ? industrial equipment pinouts isl88705, isl88706 (8 ld soic) (pdip - no longer available) top view isl88716, isl88813 (8 ld soic) (pdip - no longer available) top view isl88707, isl88708 (8 ld soic) (pdip - no longer available) top view 1 2 3 4 8 7 6 5 v dd gnd pfi wdo rst wdi pfo mr 1 2 3 4 8 7 6 5 v dd gnd pfi wdo rst wdi pfo mr 1 2 3 4 8 7 6 5 v dd gnd pfi rst rst c por pfo mr
isl88705, isl88706, isl88707, isl88708, isl88716, isl88813 fn8092 rev 6.00 page 2 of 16 november 30, 2015 ordering information part number (note) part marking v th temp range (c) package (rohs compliant) pkg. dwg. # ISL88705IP846Z (no longer available, recommended replacement: isl88705ib846z) 88705 i46z 4.64v -40 to +85 8 ld pdip** mdp0031 isl88813ip846z (no longer available, recommended replacement: isl88813ib846z) 88813 i46z 4.64v -40 to +85 8 ld pdip** mdp0031 isl88707ip846z (no longer available, recommended replacement: isl88707ib846z) 88707 i46z 4.64v -40 to +85 8 ld pdip** mdp0031 isl88706ip844z (no longer available, recommended replacement: isl88706ib844z) 88706 i44z 4.38v -40 to +85 8 ld pdip** mdp0031 isl88708ip844z (no longer available, recommended replacement: isl88708ib844z) 88708 i44z 4.38v -40 to +85 8 ld pdip** mdp0031 isl88706ip831z (no longer available, recommended replacement: isl88706ib831z) 88706 i31z 3.09v -40 to +85 8 ld pdip** mdp0031 isl88708ip831z (no longer available, recommended replacement: isl88708ib831z) 88708 i31z 3.09v -40 to +85 8 ld pdip** mdp0031 isl88706ip829z (no longer available, recommended replacement: isl88706ib829z) 88706 i29z 2.92v -40 to +85 8 ld pdip** mdp0031 isl88708ip829z (no longer available, recommended replacement: isl88708ib829z) 88708 i29z 2.92v -40 to +85 8 ld pdip** mdp0031 isl88706ip826z (no longer available, recommended replacement: isl88706ib826z) 88706 i26z 2.63v -40 to +85 8 ld pdip** mdp0031 isl88716ip826z (no longer available, recommended replacement: isl88716ib826z) 88716 i26z 2.63v -40 to +85 8 ld pdip** mdp0031 isl88708ip826z (no longer available, recommended replacement: isl88708ib826z) 88708 i26z 2.63v -40 to +85 8 ld pdip** mdp0031 isl88705ib846z* 88705 i46z 4.64v -40 to +85 8 ld soic m8.15 isl88813ib846z* 88813 i46z 4.64v -40 to +85 8 ld soic m8.15 isl88707ib846z* 88707 i46z 4.64v -40 to +85 8 ld soic m8.15 isl88706ib844z* 88706 i44z 4.38v -40 to +85 8 ld soic m8.15 isl88708ib844z* 88708 i44z 4.38v -40 to +85 8 ld soic m8.15 isl88706ib831z* 88706 i31z 3.09v -40 to +85 8 ld soic m8.15 isl88708ib831z* 88708 i31z 3.09v -40 to +85 8 ld soic m8.15 isl88706ib829z* 88706 i29z 2.92v -40 to +85 8 ld soic m8.15 isl88708ib829z* 88708 i29z 2.92v -40 to +85 8 ld soic m8.15 isl88706ib826z* 88706 i26z 2.63v -40 to +85 8 ld soic m8.15 isl88716ib826z* 88716 i26z 2.63v -40 to +85 8 ld soic m8.15 isl88708ib826z* 88708 i26z 2.63v -40 to +85 8 ld soic m8.15 isl88705eval1 evaluation board *add -tk suffix for tape and reel packaging. please refer to tb347 for details on reel specifications. **pb-free pdips can be used for through-hole wave solder proces sing only. they are not intended for use in reflow solder proce ssing applications. note: these intersil pb-free plastic packaged products employ sp ecial pb-free material sets, molding compounds/die attach mater ials, and 100% matte tin plate plus anneal (e3 termination finish, which is ro hs compliant and compatible with both snpb and pb-free solderin g operations). intersil pb-free products are msl classified at pb-free peak re flow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020.
isl88705, isl88706, isl88707, isl88708, isl88716, isl88813 fn8092 rev 6.00 page 3 of 16 november 30, 2015 functional block diagrams v ref v dd por gnd wdt v ref pfi wdi pb wdo pf pfo mr rst isl88705, isl88706 v ref v dd por gnd wdt v ref pfi wdi pb wdo pf pfo mr rst isl88716, isl88813 v ref v dd por gnd v ref pfi pb pf pfo mr isl88707, isl88708 rst rst c por osc
isl88705, isl88706, isl88707, isl88708, isl88716, isl88813 fn8092 rev 6.00 page 4 of 16 november 30, 2015 pin descriptions isl88705, isl88706 isl88716, isl88813 isl88707, isl88708 name description 111mr manual reset input. a reset signal is generated w hen this input is pulled low. the mr input is an active low debounced input to which a user can connect a push-b utton to add manual reset capability or drive with a signal. the mr pin has an internal 20k ?? pull-up. 222v dd power supply terminal. the voltage at this pin is compared against an internal factory -programmed voltage trip point, v th1 . a reset is first asserted when the device is initially powere d up to ensure that the power supply has stabilized. thereafter, reset is again ass erted whenever v dd falls below v th1 . the device is designed with hyste resis to help prevent chatteri ng due to noise and is immune to brief power-supply transients. the voltage threshold v th1 is specified in the part number suffix. 333gnd ground connection 444pfi power-fail input this is an auxiliary monitored voltage input with a 1.25v thre shold that causes pfo state to follow the pfi input state. 555pfo power-fail output. this output goes high if the voltage on pfi is greater than 1. 25v, otherwise pfo stays low. 6c por adjustable por time-out delay input. connecting an external capacitor from c por to ground allows the user to increase t he power-on reset time-out (t por ) from the nominal 200ms. 66 wdi watchdog input. the watchdog input takes an inpu t from a microprocessor and en sures that it periodically toggles the wdi pin, o therwise the internal nomina l 1.6s watchdog timer runs out, then reset is asserted and wdo is pulled low. the internal watchdog timer is cleared whenever the wdi sees a rising or falling edge or the device is manually reset. floating wdi or connecting wdi to a high-impedance three-state buffer disables the watchdog feature . 77rst active-low reset output. the rst output is an active low output with an internal pmos pull-up that is pulled low to gnd when reset is asserted. reset is asse rted whenever: 1. the device is first powered up 2. v dd falls below its minimum voltage sense level or 3. mr is asserted. the reset output continues to be asserted for typically 200ms a fter v dd rises above the reset threshold or mr input goes from low to high. a watchdog time-out will not trig ger a reset unless wdo is connected to mr . 78rst active-high reset output. the rst pin functions identical ly to its complementary rst output but is an active high push-pull output. rst is set high to v dd when reset is asserted. see the rst in pin descriptions on page 4 for more details on conditions that caus e a reset. 88 wdo watchdog output . this output is pulled low when the nominal 1.6s internal watc hdog timer expires and periodically resets until t he watchdog is cleared. wdo also goes low during low v dd conditions. whenever v dd is below the reset threshold, wdo stays low. however, unlike r eset, wdo does not have a minimum pulse width. as soon as v dd rises above the reset th reshold, wdo goes high with no delay.
isl88705, isl88706, isl88707, isl88708, isl88716, isl88813 fn8092 rev 6.00 page 5 of 16 november 30, 2015 absolute maximum ratings thermal information temperature under bias . . . . . . . . . . . . . . . . . . . . .-40c to +125c storage temperature . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c voltage on any pin with respect to gnd . . . . . . . . . . . -1. 0v to +7v dc output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5ma recommended operating conditions temperature range (industrial) . . . . . . . . . . . . . . . . . -40c to +85c thermal resistance (typical, note 1) ? ja (c/w) pdip package* (4-layer test board) . . . . . . . . . . . . . 83 soic package (4-layer test board) . . . . . . . . . . . . . 11 0 pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp *pb-free pdips can be used for through hole wave solder process ing only. they are not intended for use in reflow solder processing applications. caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. note: 1. ? ja is measured with the component mounted on a high effective the rmal conductivity test board in free air. see tech brief tb379 for details. electrical specifications over the recommended operating c onditions unless otherwise spec ified. parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. te mperature limits establis hed by characterization and are not production tested. symbol parameter conditions min typ max units v dd supply voltage range 2.0 5.5 v i dd v dd = 5v, wdt inactive 10 19 a v dd = 3v, wdt inactive 8 10 a i li input leakage current (pfi) 100 na i lo output leakage current 100 na voltage thresholds v th1 fixed v dd voltage trip point 4.556 4.640 4.724 v 4.301 4.380 4.459 v 3.034 3.090 3.146 v 2.867 2.920 2.973 v 2.583 2.630 2.677 v v th1hyst hysteresis at v th1 input temperature = +25c v th1 = 4.64v 46 mv v th1 = 4.38v 44 mv v th1 = 3.09v 37 mv v th1 = 2.92v 29 mv v th1 = 2.63v 31 mv rst and rst v ol reset output voltage low v dd ? 3.3v, sinking 2.5ma 0.05 0.40 v v dd < 3.3v, sinking 1.5ma 0.05 0.40 v v oh rst output voltage high v dd ? 3.3v, sourcing 2.5ma v dd - 0.6 v dd - 0.4 v v dd < 3.3v, sourcing 1.5ma v dd - 0.6 v dd - 0.4 v rst output voltage high v dd ? 3.3v, sourcing 0.8ma v dd - 0.6 v dd - 0.4 v v dd < 3.3v, sourcing 0.5ma v dd - 0.6 v dd - 0.4 v t rpd v th to reset asserted delay 45 s t por por time-out delay c por is open 140 200 260 ms c load load capacitance on reset pins 5 pf
isl88705, isl88706, isl88707, isl88708, isl88716, isl88813 fn8092 rev 6.00 page 6 of 16 november 30, 2015 principles of operation the isl88705, isl88706, isl8870 7, isl88708, isl88716, isl88813 devices provide t hose functions needed for monitoring critical voltages su ch as power-supply and battery functions in microprocessor systems. features of these supervisors include power-on reset control, supply voltage supervision, power-fail de tection and manual reset assertion. the integration of al l these features along with hig h reset threshold accu racy and low power consumption make these devices ideal for portable or battery -powered equipment. power-on reset (por) applying power to the device act ivates a por circuit which asserts reset (i.e. rst goes high while rst goes low). these signals provide several benefits: ? it prevents the system micropr ocessor from starting to operate with insuff icient voltage. ? it prevents the processor from operating prior to stabilizatio n of the oscillator. ? it ensures that the monitored device is held out of operation until internal registers are properly loaded. ? it allows time for an fpga to download its configuration prior to initialization of the circuit. the reset signals remain active until v dd rises above the minimum voltage sense le vel for time period t por . this ensures that the supply voltage has stabilized to sufficient operating levels. manual reset v mrl mr input voltage low 0.8 v v mrh mr input voltage high v dd - 0.6 v t mr mr minimum pulse width 550 ns r pu internal mr pull-up resistor 20 k ? watchdog timer (note 2) t wdt watchdog time-out period 1.0 1.6 2.0 s t wdps wdi minimum pulse width 100 ns v il watchdog input voltage low 0.3 x v dd v v ih watchdog input voltage high 0.7 x v dd v v wdol wdo output voltage low v dd ? 3.3v, sinking 2.5ma 0.05 0.40 v v dd < 3.3v, sinking 1.5ma 0.05 0.40 v v wdoh wdo output voltage high v dd ? 3.3v, sourcing 2.5ma v dd - 0.6 v dd - 0.4 v v dd < 3.3v, sourcing 1.5ma v dd - 0.6 v dd - 0.4 v i wdt watchdog input current 1a power-fail detection v thpfi pfi input threshold voltage mr = open 1.20 1.25 1.30 v pfiv thhyst hysteresis voltage 20 mv v pfol pfo output voltage low v dd ? 3.3v, sinking 2.5ma 0.05 0.40 v v dd < 3.3v, sinking 1.5ma 0.05 0.40 v v pfoh pfo output voltage high v dd ? 3.3v, sourcing 2.5ma v dd - 0.6 v dd - 0.4 v v dd < 3.3v, sourcing 1.5ma v dd - 0.6 v dd - 0.4 v note: 2. applies to isl88705, isl88706, isl88716, and isl88813. electrical specifications over the recommended operating c onditions unless otherwise spec ified. parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. te mperature limits establis hed by characterization and are not production tested. (continued) symbol parameter conditions min typ max units
isl88705, isl88706, isl88707, isl88708, isl88716, isl88813 fn8092 rev 6.00 page 7 of 16 november 30, 2015 low voltage monitoring these devices monitor both the voltage level of v dd and an auxiliary voltage on pfi. when ic is initially biased reset is asserted until the v dd voltage is greater than the specif ic ic fixed-voltage trip poin t for the t por duration of 200ms. at any subsequent time that v dd does not exceed its voltage threshold, reset is once again asserted, i.e. rst is high and rst is low (see figure 1). . power failure monitor these devices also have a power-failure monitor that helps to monitor an additiona l critical voltage on the power-fail input (pfi) pin. for example, the pfi pin c ould be used to provide an early power-fail wa rning, detect a low-battery condition, presence detecti on or simply monitor a power supply other than +5v. the 1.2 5v threshold detector can be adjusted using an external resis tor divider network to provide custom voltage monitoring of voltages great er than 1.25v, according to equation 1 (see figure 2). pfo goes low whenever pfi is less than the 1.25v (or user-set) threshold voltage. . if using a voltage divider on the pfi input to critique an external voltage and intending to use the mr input to initiate resets then avoid having the pf i voltage less than pfi vth +2.2v as unintended pfo tra nsition may occur when mr is transitioning high. adjusting t por on the isl88707 and isl8870 8, users can adjust the power-on reset time-out delay (t por ) to many times the nominal t por of 200ms. to do this, connect a capacitor between c por and ground (see figure 3). for example, connecting a 50pf capacitor to cpor will increase t por from 200ms to ~1.4s. care should be taken in pcb layout and capacitor placement in order t o reduce stray capacitance as much as possible, whi ch contributes to t por error. figure 1. power-supply monitoring timing diagram (wdi tri-stated ) v dd mr rst t por v th1 1v t por t por >t mr t rpd rst pfi v th 1.25 r 1 r 2 + r 2 -------------------- - ?? ?? ?? = (eq. 1) figure 2. custom v th with resistor divider on pfi v in r 1 r 2 pfi isl8870x
isl88705, isl88706, isl88707, isl88708, isl88716, isl88813 fn8092 rev 6.00 page 8 of 16 november 30, 2015 . manual reset the manual-reset input (mr ) allows the use r to trigger a reset by using a push-button switch. the mr input is an active low debounced input. by connecting a push-button directly from mr to ground, the designer adds manual system reset capabilit y (see figure 4). re set is asserted if the mr pin is pulled low to less than 100mv for the minimum mr pulse width or longer while t he push-button is closed. after mr is released, the reset ou tputs remain asserted for t por (200ms) and then released. watchdog timer the watchdog timer circuit c hecks microprocessor activity by monitoring the wdi input pi n. the microprocessor must periodically toggle the wdi pin within t wdt (typically ~1.6s), otherwise the wdo pin pulls low (see figure 5). the wdo then signals reset periodically (typically ~1.9s) for ~220ms until the wdi is again toggled. i nternally, the 1.6s timer is cleared by either a reset or by toggling the wdi input, which can detect pulses longer than 50ns. whenever there is a low-voltage v dd condition, wdo goes low. unlike the reset outputs, however, wdo does not have a minimum reset pulse width (t por ). wdo goes high as soon as v dd rises above its voltage trip point (see figure 5). with wdi open or connected to a tristated high impedance input, the watchdog timer is di sabled and only pulls low when v dd < v th1. isl88707, isl88708 figure 3. adjusting t por with a capacitor c por (pf) c por 0 2 4 6 8 10 12 14 0102030405060708090100 normalized t por vs c por (pf) open = 200ms mr pb 20k figure 4. connecting a manual reset push-button isl8870x
isl88705, isl88706, isl88707, isl88708, isl88716, isl88813 fn8092 rev 6.00 page 9 of 16 november 30, 2015 figure 5. watchdog timing diagram v dd wdi wdo v th1 1v t wdt >t wdps < t wdt < t wdt < t wdt t por t rpd rst t por t wdt t por typical performance curves figure 6. i dd vs temperature figure 7. v th1 vs temperature for 5v supply figure 8. v th1 vs temperature < 5v supply figure 9. v thpfi vs temperature 6.00 6.50 7.00 7.50 8.00 8.50 9.00 9.50 10.0 10.5 -40-30-20-10 0 1020304050607090 temperature (c) i dd (a) 11.0 v dd = 3.3v v dd = 5v 4.20 4.25 4.30 4.36 4.40 4.45 4.50 4.55 4.60 4.65 -40-30-20-10 0 1020304050607090 temperature (c) v th1 (v) 4.70 v th = 4.64v v th = 4.38v -40-30-20-10 0 1020304050607090 temperature (c) v th1 (v) 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 v th = 2.92v v th = 3.09v v th = 2.63v temperature (c) 1.2530 1.2525 1.2520 1.2515 1.2510 1.2505 1.2500 v thpfi (v) -40-30-20-10 0 1020304050607090
isl88705, isl88706, isl88707, isl88708, isl88716, isl88813 fn8092 rev 6.00 page 10 of 16 november 30, 2015 figure 10. reset and reset assertion figure 11. reset assertion vs cpor figure 12. reset and reset deassertion figure 13. 5v pfi to pfo response typical performance curves (continued) v dd reset reset c por = open t por = 213ms v dd reset 50pf 1.5s open 172ms 4.7pf 312ms 15pf 588ms 33pf 1.1s v dd reset reset pfo pfi pfi v th
isl88705, isl88706, isl88707, isl88708, isl88716, isl88813 fn8092 rev 6.00 page 11 of 16 november 30, 2015 isl88705eval1 and applications the isl88705eval1 supports all six of t he isl88705, isl88706, isl88707, isl 88708, isl88716, isl88813 devices, enabling evaluation o f basic functional operation and common application impl ementations. figures 15 and 17 illustrate the isl88705e val1 in photographic and schematic forms respectively. the isl88705eval1 is divide d into two banks; each bank having one each of the three available pinouts. the top bank is fully populated and immediately usable whereas the bottom bank is unpopulated. samples of other sample variants can be evaluated singul arly or in combination with any other variant to provide a specific voltage monitoring solution. the left position has the isl88705ib846z monitoring the v dd rail voltage for a mi nimum of 4.64v with reset signaling. in addition, the power fail input (pfi) is bei ng compared to the internal pfi voltage reference of 1.25v and the power fail output (pfo ) will report the pfi condition. this feature can be used for monitoring an au xiliary voltage, providing an early warning of a brown-out or power failure or presence detecti on in a system. the middle position has the isl88813ib846z installed and is set-up as a 5v window detector with jumper j1 installed. the v dd monitors for uv and the pfi for ov via the r 3 , r 4 divider. the pfo output is inverted and connected to the manual reset input (mr) via u4. hence, a reset signal is generated when 4.64v < v dd > 5.38v. with j1 removed, the pfo will be an ov indicator but no reset signal will be generated. both of these positions share a common watchdog input (wdi) signal although each has its own watchdog output (wdo ). the right position has the isl88707ib846z and is set-up as a +12v and +5v uv m onitor with reset signal. the pfi allows monitoring of any voltage above the 1.25v pfi reference and with a resistor d ivider this is used to monitor the 12v. the isl88707 and isl88708 have the unique feature of an adjusta ble time to reset (t por ) signal generation capability via the c por pin with an external capacitor to gnd. this evaluation platform has an adjustable smd capacitor, c 4 (8pf to 45pf) that allows easy evaluation of this feature. also unique to the isl88707 and isl88708 are both the reset and reset outputs, all other variants having only one or the other. figures 10, 11, 12, 13 and 14 illu strate the basic ic functions and performance of the 3 implementations. figure 14. 5v ov/uv monitoring typical performance curves (continued) reset v dd 5.5v ov figure 15. isl88705eval1
isl88705, isl88706, isl88707, isl88708, isl88716, isl88813 fn8092 rev 6.00 page 12 of 16 november 30, 2015 bipolar voltage sensing any of the isl88705, isl88706, isl88707, isl88708, isl88716, isl88813 devices can be used to sens e and report the presence of both a positiv e and negative vo ltage via the pfi and pfo, as shown in fi gure 16. the v dd monitors the positive voltage as normal and the pfi monitors the presence of the negative supply. as the d ifferential voltage across the r 1 , r 2 divider is increased, the resistor values must be chosen such that the pfi node is < 1.25v when the -v supply is satisfactory and the positive supply is at its maximum specifie d value. this allows the positive supply to fluctuate within its acceptable range without signaling a reset. driving the mr with the inverted pfo signal as shown provides for reset generation when -v is not sati sfactorily present. reset will remain asserted as long as pfo is high. special application considerations using good decoupling practice s will prevent transients (i.e., due to switching noises and short duration droops in the supply voltage) from c ausing unwanted resets. when using the c por pin, avoid stray capacitance during layout as much as possible in order to minimize its effect on t he t por timing. if using a voltage resistor divider on the pfi input to critiqu e an external voltage and intending to use the mr input to initiate resets then avoid having the pf i voltage less than pfi vth +2.2v as unintended pfo tra nsition may occur when mr is transitioning high. figure 16. 5v monitoring +5v isl8870x, isl88716, isl88813 -5v 100k 100k 2n3904 mr rst pfo pfi r1 r2 v+ v- reset v dd
isl88705, isl88706, isl88707, isl88708, isl88716, isl88813 fn8092 rev 6.00 page 13 of 16 november 30, 2015 figure 17. isl88705eval1 schematic (top bank)
fn8092 rev 6.00 page 14 of 16 november 30, 2015 isl88705, isl88706, isl88707, isl88708, isl88716, isl88813 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas llc 2005-2015. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. about intersil intersil corporation is a leading provider of innovative power management and precision analog solutions. the company's produc ts address some of the largest marke ts within the industrial and i nfrastructure, mobile computing and high-end consumer markets. for the most updated datasheet, application no tes, related documentation and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggesti ons for improving this datashe et by visiting www.intersil.com/ask . reliability reports are also a vailable from our website at www.intersil.com/support revision history the revision history provided is for informational purposes onl y and is believed to be accurate, but not warranted. please go to the web to make sure that you have the latest revision. date revision change november 30, 2015 fn8092.6 updated ordering information table on page 2. added revision history and about intersil sections. updated package outline drawing m8.15 to the latest revision. changes are as follows: -updated to new pod format by removing table and moving dimensions onto drawing and adding land pattern. -changed in typical recommended land pattern the following: 2.41(0.095) to 2.20(0.087) 0.76 (0.030) to 0.60(0.023) 0.200 to 5.20(0.205) -changed note 1 ?1982? to ?1994?.
isl88705, isl88706, isl88707, isl88708, isl88716, isl88813 fn8092 rev 6.00 page 15 of 16 november 30, 2015 plastic dual-in-line packages (pdip) mdp0031 plastic dual-in-line package symbol inches tolerance notes pdip8 pdip14 pdip16 pdip18 pdip20 a 0.210 0.210 0.210 0.210 0.210 max a1 0.015 0.015 0.015 0.015 0.015 min a2 0.130 0.130 0.130 0.130 0.130 0.005 b 0.018 0.018 0.018 0.018 0.018 0.002 b2 0.060 0.060 0.060 0.060 0.060 +0.010/-0.015 c 0.010 0.010 0.010 0.010 0.010 +0.004/-0.002 d 0.375 0.750 0.750 0.890 1.020 0.010 1 e 0.310 0.310 0.310 0.310 0.310 +0.015/-0.010 e1 0.250 0.250 0.250 0.250 0.250 0.005 2 e 0.100 0.100 0.100 0.100 0.100 basic ea 0.300 0.300 0.300 0.300 0.300 basic eb 0.345 0.345 0.345 0.345 0.345 0.025 l 0.125 0.125 0.125 0.125 0.125 0.010 n 8 14 16 18 20 reference rev. c 2/07 notes: 1. plastic or metal protrusions of 0.010? maximum per side are not included. 2. plastic interlead protrusions of 0.010? maximum per side are not included. 3. dimensions e and ea are measured with the leads constrained perpendicular to the seating plane. 4. dimension eb is measured wi th the lead tips unconstrained. 5. 8 and 16 lead packages have half end-leads as shown. d l a e b a1 note 5 a2 seating plane l n pin #1 index e1 12 n/2 b2 e eb ea c
isl88705, isl88706, isl88707, isl88708, isl88716, isl88813 fn8092 rev 6.00 page 16 of 16 november 30, 2015 package outline drawing m8.15 8 lead narrow body small outline plastic package rev 4, 1/12 detail "a" top view index area 123 -c- seating plane x 45 notes: 1. dimensioning and tolerancing per ansi y14.5m-1994. 2. package length does not include mold flash, protrusions or ga te burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm ( 0.006 inch) per side. 3. package width does not include interlead flash or protrusions . interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 4. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 5. terminal numbers are s hown for reference only. 6. the lead width as measured 0.36m m (0.014 inch) or greater abo ve the seating plane, shall not exceed a maximum value of 0.61mm (0.02 4 inch). 7. controlling dimension: millimete r. converted inch dimensions a re not necessarily exact. 8. this outline conforms to je dec publication ms-012-aa issue c . side view a side view b 1.27 (0.050) 6.20 (0.244) 5.80 (0.228) 4.00 (0.157) 3.80 (0.150) 0.50 (0.20) 0.25 (0.01) 5.00 (0.197) 4.80 (0.189) 1.75 (0.069) 1.35 (0.053) 0.25(0.010) 0.10(0.004) 0.51(0.020) 0.33(0.013) 8 0 0.25 (0.010) 0.19 (0.008) 1.27 (0.050) 0.40 (0.016) 1.27 (0.050) 5.20(0.205) 1 2 3 4 5 6 7 8 typical recommended land pattern 2.20 (0.087) 0.60 (0.023)

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